This application is based on and claims priority of Japanese patent application 2000-398509, filed on Dec. 27, 2000, all of the contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor memory device and a method of manufacturing the same, and in particular, to a semiconductor memory device including stacked gate electrodes of which each includes a floating gate electrode and a control gate and a method of manufacturing the same.
2. Description of the Related Art
With development of the information society, a need exists to further increase the integration density of semiconductor memory devices. A flash memory includes a stack of a floating gate and a control gate above a channel region to form a non-volatile memory and hence does not require the refresh operation. Thanks to the advantage that the refresh operation is not required, the flash memory is employed in many electronic apparatuses. For a higher integration density and for a lower operation voltage of the flash memory, it is desired to lower the writing and erasing voltages.
In a flash memory, it is necessary for carriers to tunnel a tunnel oxide film of about 10 nanometer (nm) thickness between a channel and the floating gate. For the tunnel operation, a voltage of about plus or minus 10 volt (V) or more (in magnitude) is required. To lower the writing and erasing voltages, it is effective to minimize the film thickness of the tunnel oxide film.
When the film thickness is lowered to about 3 nm, the voltage necessary for carriers to tunnel the tunnel oxide film can be reduced to about plus or minus 5 V.
However, when the film thickness of the tunnel gate oxide film is minimized, carriers accumulated in the floating gate easily tunnel to extension region of the source/drain region applied with a relatively high voltage. This resultantly reduces the retention time for retaining carriers in the floating gate of the memory device.
A need exists for a semiconductor memory device in which the voltage for operating the device is lowered without reducing the information retention time.
It is therefore an object of the present invention to provide a semiconductor memory device in which the thickness of the tunnel oxide film can be reduced and the deterioration of the retention time can be reduced.
Another object of the present invention is to provide a method of manufacturing a semiconductor memory device of this kind.
According to one aspect of the present invention, there is provided a semiconductor memory device, comprising a semiconductor substrate including an active region of first conductive type; a gate insulating layer formed on said active region, said gate insulating layer including a thin central section and thick end section on each side thereof; a floating gate electrode formed on said gate insulating layer;
an inter-electrode insulating layer formed on said floating gate electrode; a control gate electrode formed on said inter-electrode insulating layer; a pair of source/drain regions of second conductive type respectively extending in said active region from respective sides of said floating gate electrode respectively below said thick end sections, said source/drain regions being apart from said thick end section.
According to one aspect of the present invention, there is provided a method of manufacturing a semiconductor memory device, comprising the steps of: (a) forming a stack of a first gate insulating layer, a floating gate electrode layer, an inter-electrode insulating layer, and a control electrode layer on a semiconductor substrate including an active region of first conductivity type; (b) patterning said stack using a mask and thereby creating a gate electrode pattern; (c) causing a chemical reaction for said gate electrode pattern from both sides thereof and forming thereby a second gate insulating layer on each side of a central section of said first gate insulating layer, said second gate insulating layer being thicker than said first gate insulating layer; and (d) implanting ions of impurity of a second conductivity type in said active regions on both sides of said gate electrode pattern and forming thereby first source/drain regions respectively extending below said second insulating layers.
Since the thickness of the gate insulating film is increased in the vicinity of the source/drain region, the amount of a tunneling leakage current from the floating gate electrode to the source/drain region is reduced.
This improves the information retaining capability of the semiconductor memory device